With continued scaling of metal oxide semiconductor (MOS) field effect transistors (FETs), the area available for making electrical contacts to doped semiconductor source/drain regions is decreasing. As a consequence, the resistance of such contacts (which are typically metal-to-semiconductor contacts) is becoming an excessively large component of the total electrical resistance of a transistor when it is switched on. This undesired metal-semiconductor contact resistance is becoming a very significant performance limiting factor for such devices, contributing both to wasted energy and reduced switching speeds (clocking rates) in digital integrated circuits comprising such transistors. Furthermore, the decreasing volume of doped source and drain regions in state of the art transistors accommodates fewer dopant atoms, even at very high doping concentrations in excess of 1020 dopants/cm3. As a consequence, the variability in transistor performance that is a result of variance in doping species number and placement is predicted to become a significant problem in future, nanometer-scale MOS transistors, particularly in anticipated, gate-all-around nanowire transistors.
FIG. 1 shows an example of a gate-all-around nanowire transistor 10. In this example, a gate wraps completely around a semiconductor channel. A gate oxide is disposed concentrically between the gate and the channel. Doped semiconductor source and drain regions are located at opposite ends of the channel and have associated circumferential contacts, typically metal silicide contacts, separated from the gate contact by an gate sidewall spacer.
Contact resistance is conventionally calculated as “contact resistivity” divided by the area of the contact. Traditionally therefore contact resistance has been minimized by ensuring as low a contact resistivity and as large a contact area as technologically possible. According to Park et al., “Scaling effect on specific contact resistivity in nano-scale metal-semiconductor contacts”, Proc. Device Research Conference (2013), however, “initial results indicate that contact resistivity increases in the limit of very small contact areas and that the effect is stronger in the 3D wire case compared to the 2D wire case.” Contact resistance of metal-semiconductor contacts is expected to increase even more than a classical model would predict in the size regime of 10 nm and smaller due to the two-fold effects of increasing resistivity and decreasing contact area. There is then a serious metal-semiconductor contact resistance problem for present and future nanoscale transistors that have contact dimensions of approximately 10 nm or less.
Furthermore, in present day, state-of-the-art transistors, at nodes smaller than 20 nm, the semiconductor channel is fully depleted, whether the transistors are fully-depleted silicon-on-insulator (FDSOI) FETs, FinFETs, “tri-gate FETs”, nanowire FETs or gate-all-around FETs. Fully depleted implies that the thickness of the semiconductor body that includes the channel and the parts of the source/drain adjoining the channel are extremely thin, typically less than 12 nm or so. The parts of the source and drain that adjoin the channel may have a very small volume. When such transistors have conventional doped source/drain regions, the number of dopant atoms in the source and drain regions proximate to the channel may be of the order of ten or fewer and these dopants will have random placement. As such, the doping in any given transistor is stochastic rather than deterministic and this can lead to excessive variability in the electrical performance of a population of transistors that form an integrated circuit.
To explain this problem in more detail, even at high doping levels in excess of 1020 dopant/cm3, the dopants are sparse, at most comprising only 2% of the atoms present in the source/drain regions and more typically less than 1%. It has been recognized that when the volume of source/drain regions is small, the statistical variation of the number and location of the dopant atoms introduces a very large variance in the electrical responses of the transistors. See, e.g., Martinez et al., “Quantum-Transport Study on the Impact of Channel Length and Cross Sections on Variability Induced by Random Discrete Dopants in Narrow Gate-All-Around Silicon Nanowire Transistors,” IEEE Trans. Electron Devices, Vol. 58, No. 8, p. 2209 (2011). In this article, the authors point out that a transistor with an unfortunate configuration of dopant atoms in source/drain can have both an undesirably high “off” current (under zero gate bias) and an undesirably low “on” current (under high gate bias) relative to a transistor with a more favorable configuration of dopant atoms. In designing an integrated circuit, often comprising several billion transistors, it is the “weak” transistors that determine the performance of the whole circuit. That is, to obtain high yields of manufactured ICs it is necessary to design the circuit assuming transistors are the inferior or weak type. Stated differently, the performance of a circuit is determined by the weakest of the transistors rather than the strongest. In modern statistical design of circuits, the dependence is more nuanced but it is generally true that given a statistical distribution of device characteristics across a large population of transistors, the performance of a circuit is determined more by the low performance of the weaker transistors than the high performance of the stronger transistors. What is preferred is to have a population of transistors with the variance in their electrical performance as small as possible.
Quite apart from the severe contact resistance problem associated with nanoscale metal-semiconductor contacts, the statistical variance of source/drain doping thus presents another major challenge to further scaling of MOS transistors into the 7 nm node and beyond. Metal source/drain transistors provide a solution to the dopant variability problem in conventional doped source/drain technologies. Dopants can be eliminated if the source/drain regions are formed of a metal that adjoins the undoped channel region and provides carriers to the channel directly without any need for doped semiconductor. Such metal source/drain regions most desirably have a small Schottky barrier height in order for their performance to be competitive with doped source/drain counterparts.
U.S. Pat. Nos. 6,833,556, 7,084,423, 7,112,478, 7,883,980, and 9,362,376, all assigned to the assignee of the present invention and each incorporated herein by reference, describe methods and structures that enable high performance metal source/drain field effect transistors. Briefly, an electrical junction includes an interface layer disposed between a contact metal and a semiconductor, and may comprise a passivation layer (which in some instances may be a monolayer) adjacent the semiconductor and, optionally, a separation layer disposed between the passivation layer and the metal. Various metals and semiconductors may be used, and the passivation layer may be an oxide of the semiconductor or other material. The separation layer, if present, may be a metal oxide. The very thin, interfacial dielectric layer between the metal and semiconductor acts to reduce the Schottky barrier at the junction from that which would exist in the absence of the interface layer, and at the same time has sufficient conductivity, despite being itself a dielectric with poor bulk electrical conduction, to provide a net improvement in the conductivity of the MIS junction. These devices overcome the statistical dopant variability problem by eliminating source/drain doping completely. However, these devices do have a remaining limitation in that the area of the metal-semiconductor interface, where a metal source or drain adjoins the semiconductor channel, is exceedingly small, being broadly comparable to the cross sectional area of the channel. U.S. Pat. No. 8,212,336 provides a solution that offers some relief to the area limitation by providing an interface that has an area exceeding the cross-sectional area of the channel.
It is known to induce “virtual” p-type and n-type regions using MOS capacitors. Such MOS capacitors are not conductive and do not provide a current to the semiconductor. The MOS capacitors induce variously (and optionally) p-type or n-type semiconductor regions. Electrical current into or out of these regions is provided by other (additional) electrical contacts. See e.g., André Heinzig et al., “Reconfigurable Silicon Nanowire Transistors”, Nano Letters, Vol. 12, pp. 119-124 (2012).
FIGS. 6A and 6B are reproduced from FIGS. 6a and 6c, respectively, of U.S. Pat. No. 6,891,234, assigned to the assignee of the present invention, and illustrate induced charge regions in various transistor configurations. In both cases “virtual extensions” are induced under “overlap M” regions of low work function metals (for n-channel devices) or high work function metals (for p-channel). An “overlap M” region is described as: “a conductor (in this case a metal) 92 that overlaps an extension region 94 between the source and/or drain regions 96 and the channel region 98. This conductor 92 is separated from the extension region 94 by an insulator 100 and is chosen to have a workfunction that will induce a desired polarity and concentration of charge in the extension region 94.” Further, the “overlap M” regions are connected to the source/drain metal regions as also described: “In illustration 6(c), transistor 113, configured in accordance with an embodiment of the present invention, has virtual extensions 114 from the n+ S/D regions 115 that result from the use of the overlapping metal 118. These metal layers 118 are connected to the metal S/D contacts 116 and are separated from the extension regions 114 and the gate 119 by an insulator 120.”
Regarding the work-functions of the overlap metals, the '234 patent states: “In one embodiment of the present invention, the conductor used to overlap the extension region is a metal possessing a low workfunction Φx in an n-channel FET. This effective workfunction is considered low when it is less than the electron affinity Xc of the semiconductor. It is generally advantageous to have Φx as low as possible. The lower the workfunction, the greater the amount of charge (in this case electrons) induced in the extension, which generally reduces the resistance of the extension region, generally advantageously increasing the drive-current capability of the transistor. In another embodiment of the present invention, the workfunction Φx of the metal is high in a p-channel FET, where Φx is greater than the hole affinity of the semiconductor (i.e., more than a bandgap greater than the semiconductor's electron affinity). The overlapping metal in this case induces holes in the extension region. It is generally advantageous to have a metal with as high a workfunction as possible. The workfunction of the metal lies outside of the semiconductor bandgap.”
Connelly et al., “Improved Short-Channel n-FET Performance with Virtual Extensions,” Abstracts of the 5th International Workshop on Junction Technology (2005) reports: “An alternative to purely doped S/D extensions is to form a charge layer electrostatically, of thickness comparable to the channel thickness of just a few nanometers. One approach, separately biased spacers, results in additional wiring complexity and capacitance. A better approach to electrostatically induced “virtual extensions” is . . . to overlay a metal of appropriate work function above the extension regions to induce such a mobile charge layer, a “virtual extension” . . . this creates a zero-bias MOS capacitor in the extension regions, where, for an n-FET, a negative VT results in a permanently induced charge layer that provides an ultra-shallow tip to conventional S/D doping profiles.” “[T]his “virtual extension” tip can reduce the electrostatic coupling between a S/D and the channel . . . . The metal in the thin “overlap metal” had a work function of 3V (n-FET), comparable to Er or Yb. The virtual extension thus provides an ultra-thin sheet of charge.” In this paper, the exemplary virtual extension structure was modeled with an “extension oxide thickness” of 0.7 nm, an identical “gate oxide thickness” of 0.7 nm and an “overlap metal effective work-function” equal to 3 V. It is implied therefore that there is no current flow between the overlap metal and the semiconductor just as there is no current flow between the gate metal and the semiconductor.
U.S. Pat. Nos. 8,586,966 and 9,123,790 describe making contacts to FinFETs and nanowire source/drains. U.S. Pat. No. 8,586,966 states: “a nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.” Doped source/drain regions are used: “The source and drain diffusion regions may include either N type (for NMOS) or P type (for PMOS) doped with, for example, As or P (N type) or B (P type) at a concentration level typically 1e19 atoms/cm3 or greater.”
Similarly, U.S. Pat. No. 9,123,790 reports on “forming a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, material of the channel layer and to provide a source terminal or drain terminal for the transistor.” “In some embodiments, forming the contact further includes epitaxially depositing an epitaxial film on the channel layer prior to depositing the metal to form the contact, the epitaxial film being configured to surround, in the at least one planar dimension, the material of the channel layer and being disposed between the material of the channel layer and material of the contact.” In the specification, various doping methods are described: “The source and drain regions may be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. The ion implantation process is typically followed by an annealing process that activates the dopants and causes them to diffuse. In the latter process, materials of the stack of layers may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with a silicon alloy such as silicon germanium or silicon carbide, thereby forming the source and drain regions. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further implementations, alternate materials may be deposited into the recesses to form the source and drain regions, such as germanium or a group III-V material or alloy.”
Fischer, S. et al., “Dopant-free complementary metal oxide silicon field effect transistors,” Phys. Status Solidi A 213, No. 6, pp. 1494-1499 (2016), report on dopant-free CMOS devices utilizing ultrathin silicon nitrides and metals with appropriate work functions to provide n- and p-type semiconductor contacts. The reported silicon nitride layers are thicker than a monolayer (e.g., on the order of 7-27 Angstroms), and there is no mention of a negative Schottky barrier between the metal contact and the semiconductor.